AAE EN0-001 Updated Exam

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Question 24

Using a Generic Interrupt Controller (GIC), when the interrupt handler writes to the End of Interrupt Register (ICCEOIR), which of the following state transitions might occur for that interrupt ID?

Options:

Inactive to Active

Pending to Active

Active to Inactive

Active to Pending

Question 25

Assuming a 4-core Cortex-A9 SMP system which does not use the Accelerator Coherency Port (ACP). and operates the L1 caches in writeback mode, in which of the following situations is a cache clean operation required?

Options:

An external DMA engine modifies data in a region of data memory which is already cached by the processor

An external agent needs to read data which has been modified by the processor in a cacheable memory region

Debugger reads data from a shared, cacheable memory location

One core modifies data in a shared cacheable memory region

Question 26

Clicking the Start button in a debugger:

Options:

Begins processor execution.

Resets the processors.

Erases existing breakpoints.

Puts the processor(s) into debug state.

Question 27

On an ARM processor that does not implement Security Extensions, which one of the following can be the starting address of the exception vector table?